1. Field of the Invention
The present invention relates to a data read-and-write controlling device that writes data in a storage unit and writes address information of the data in a table, and reads data from the storage unit by referring to the address information written in the table.
2. Description of the Related Art
In recent years, in RAM read-and-write controlling device, a single-port RAM using a common address port at the time of writing and reading has been used. See for example Japanese Patent Application Laid-open Publication No. 2005-258485. Such a conventional RAM read-and-write controlling device confirms that data is written in a RAM, and then writes, in a table, address information indicative of an address of data written in the RAM. The RAM read-and-write controlling device then reads the written address information, and by referring to the read address information, reads the data from the RAM.
A conventional RAM read-and-write controlling device is specifically explained below by using FIGS. 10 to 13. FIG. 10 is a block diagram of the structure of the conventional read-and-write controlling device. FIG. 11 is a structural diagram of a RAM write-information table included in the conventional RAM read-and-write controlling device. FIG. 12 is a time chart of a process flow of the conventional RAM read-and-write controlling device when data is input to a write controlling unit (WCTL0 ). FIG. 13 is a time chart of a process flow of the conventional RAM read-and-write controlling device when data is simultaneously input to a plurality of write controlling units (WCTL0 and WCTL1).
First, by using FIG. 10, the process of writing address information in a table is explained. As depicted in FIG. 10, the conventional data read-and-write controlling device includes a plurality of registers, such as S30, WA_S30, and WREQ, in a write controlling unit (WCTL). These registers retain various pieces of information for writing in the RAM. Such data can be data to be written in the RAM, an address indicative of a location where the data is written, and write request information (WREQ) for making a request for writing data.
The conventional data read-and-write controlling device also includes a plurality of registers between the RAM and the write controlling unit for temporarily storing various pieces of information before that information is stored in the RAM. Such registers include a write data register (WDR), an address data register (ADR), a write enable register (WER), and a clock-enable register (CER). The information that is stored in these registers includes data, address, write-enable information (WE), and clock-enable information (CE).
In the conventional data read-and-write controlling device, the write controlling unit notifies an arbitrating circuit of data write request information (for example, WREQ=1). When an access right from the arbitrating circuit to the RAM is assigned to the write controlling unit that issued a write request, data and addresses stored in registers S30 and WA_S30 (for example, data “HD+4B” and an address “0”) are written in the relevant registers (WDR and ADR). Then, the conventional data read-and-write controlling device refers to the information (AD, WE, and CE) stored in the respective registers (ADR, WER, and CER) to write the address information in a RAM write-information table.
The conventional RAM write-information table is explained in detail below by using FIG. 11. As explained above, by referring to the information stored in the registers (ADR, WER, and CER), the conventional RAM write-information table writes the address information in the RAM write-information table.
That is, in the conventional data read-and-write controlling device, as depicted in FIG. 11, when the RAM is accessed (CE=“1”), the address stored in ADR is input to a decoder in the table. Also, when a value of CE (CE=1) stored in CER is input, an enable signal of a register in a target table becomes EN=“1” with logical multiplication.
Then, in the conventional data read-and-write controlling device, the value of WE stored in WER (“1” for write and “0” for read) when EN=“1” is obtained is input to a register in the table. The input value of WE is then associated with an address stored in the decoder. The result is then stored as address information (for example, [0]=“1”) in the register.
Next, by using FIGS. 12 and 13, process timing of the conventional RAM write-information table is explained. Specifically, process timing explained below is from the time when, after the conventional RAM write-and-read controlling device confirms that data is written in the RAM (that is, the values of WE and CE become “1”), the address information indicative of an address of the data to be written in the RAM is written in the table to the time when the data is read from the RAM by referring to the read address information.
That is, as depicted in FIG. 12, the conventional RAM read-and-write controlling device retains data (HD+4B) in WDR, and retains the value of WAS30 (=“0”) in ADR. After the values of WE and CE are changed to “1”, ADR=“0”, “WE”=“1”, and CE=“1” stored in WER and CER are input to the RAM write-information table, with the address information being changed to table “0”=“1”.
Then, the conventional RAM read-and-write controlling device reads the address information (table “0”=“1”) stored in the RAM write-information table, and reads the data from the RAM by referring to the address information.
FIG. 13 depicts the process when data is simultaneously input to a plurality of write controlling units (WCTL0 and WCTL1). As with FIG. 12, after it is confirmed that data is written in the RAM, address information indicative of an address of the data written in the RAM is written in a table.
However, in the conventional technology, address information is not written until it is confirmed that data is written in the RAM. Because the data is not read from the RAM until the address information is written, it leads to greatly lowering the latency.